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Proceedings of the 8th Argentine Symposium on Computing Technology (AST), 36 JAIIO - Novel FPGA based Floating Point Multiplier: Consecutive-Sums Sequential Multiplier

Congreso

Autoría
MARCOS FUNES, ; CARRICA, DANIEL OSCAR ; MARIO BENEDETTI, ; PATRICIO DONATO,
Fecha
2007
Editorial y Lugar de Edición
JAIIO
ISSN
1850-2776
Resumen Información suministrada por el agente en SIGEVA
FPGA based Floating Point Multipliers of Parallel type demand abundant logical resources. On the other hand, Sequential type, required reduced logic resources but al the expense of a worse processing speed. This paper presents a new sequential structure of floating-point multiplier with a better processing speed keeping on a reduced number of resources.
Palabras Clave
Punto FlotanteMultiplicadoresFPGA